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< Page ,Total 10 >
Resistive switching characteristics of Ni/HfO2/Pt ReRAM EI Scopus CSCD
期刊论文 | 2012 , 33 (5) | Journal of Semiconductors
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Abstract :

This study investigated the resistive switching characteristics of the Ni/HfO2/Pt structure for nonvolatile memory application. The Ni/HfO2/Pt device showed bipolar resistive switching (RS) without a forming process, and the formation and rupture of conducting filaments are responsible for the resistive switching phenomenon. In addition, the device showed some excellent memory performances, including a large on/off ratio (> 3 × 105), very good data retention (> 103 s @ 200 °C) and uniformity of switching parameters. Considering these results, the Ni/HfO2/Pt device has the potential for nonvolatile memory applications. © 2012 Chinese Institute of Electronics.

Keyword :

Conducting filament Conductive filaments Forming process Good data HfO2 Memory performance Non-volatile memory application On/off ratio Programmable metallization cells Resistive random access memory Resistive switching Switching parameters

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GB/T 7714 Zhang, Xiao . Resistive switching characteristics of Ni/HfO2/Pt ReRAM [J]. | Journal of Semiconductors , 2012 , 33 (5) .
MLA Zhang, Xiao . "Resistive switching characteristics of Ni/HfO2/Pt ReRAM" . | Journal of Semiconductors 33 . 5 (2012) .
APA Zhang, Xiao . Resistive switching characteristics of Ni/HfO2/Pt ReRAM . | Journal of Semiconductors , 2012 , 33 (5) .
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A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering EI Scopus CSCD
期刊论文 | 2011 , 32 (8) | Journal of Semiconductors
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A CMOS wideband front-end IC is demonstrated in this paper. It consists of a low noise transconductance amplifier (LNTA) and a direct RF sampling mixer (DSM) with embedded programmable discrete-time filtering. The LNTA has the features of 0.5-6 GHz wideband, wideband input matching and low noise. The embedded filter following the DSM operates in discrete-time charge domain, filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency. The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz. It shows a conversion gain of 12.6 dB and IP1dB of -7.5 dBm at 2.4 GHz. It occupies a chip area of 0.23 mm2 and consumes 14 mA DC current. © 2011 Chinese Institute of Electronics.

Keyword :

Discrete time DSM FIR filtering IIR LNTA Wide-band windowed integration

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GB/T 7714 Xu, Jiangtao , Saavedra, Carlos E. , Chen, Guican . A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering [J]. | Journal of Semiconductors , 2011 , 32 (8) .
MLA Xu, Jiangtao 等. "A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering" . | Journal of Semiconductors 32 . 8 (2011) .
APA Xu, Jiangtao , Saavedra, Carlos E. , Chen, Guican . A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering . | Journal of Semiconductors , 2011 , 32 (8) .
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A new structure of substage in pipelined analog-to-digital converters EI Scopus CSCD
期刊论文 | 2009 , 16 (1) , 86-90 | Journal of China Universities of Posts and Telecommunications
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The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators' decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2. © 2009 The Journal of China Universities of Posts and Telecommunications.

Keyword :

Analog signals Decision levels Digital correction International corporation Pipelined ADCs Pipelined analog-to-digital converter Residue voltage Transition errors

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GB/T 7714 JIA, Hua-yu , CHEN, Gui-can , ZHANG, Hong . A new structure of substage in pipelined analog-to-digital converters [J]. | Journal of China Universities of Posts and Telecommunications , 2009 , 16 (1) : 86-90 .
MLA JIA, Hua-yu 等. "A new structure of substage in pipelined analog-to-digital converters" . | Journal of China Universities of Posts and Telecommunications 16 . 1 (2009) : 86-90 .
APA JIA, Hua-yu , CHEN, Gui-can , ZHANG, Hong . A new structure of substage in pipelined analog-to-digital converters . | Journal of China Universities of Posts and Telecommunications , 2009 , 16 (1) , 86-90 .
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Clock and data recovery circuit based on DVI EI Scopus CSCD
期刊论文 | 2008 , 29 (7) , 1417-1421 | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors
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Abstract :

A novel clock and data recovery circuit has been designed to implement a digital visual interface (DVI) receiver. A flexible buffer was placed between the over-sampler and DPLL. Not only was 10 bits data recovery implemented, but also the frequency of sampling clock was reduced to 2.5 times of the data frequency. The phase verification for 10 bit parallel data by DPLL increases the accuracy rate of judgment and improves the bit error rate. The receiver has been fabricated with an SMIC 0.18 μm CMOS process. The testing results show that the maximum peak-peak and RMS jitters of the output system clock are 183 ps and 24 ps, respectively, under the measuring condition that the data rate is 1.65 Gbps/ch for inputting a UXGA pixel data signal with 2 m cable.

Keyword :

Accuracy rate Clock and data recovery Data recovery DPLL Measuring conditions Over-sampler Sampling clocks Visual Interface

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GB/T 7714 Xiao, Jian , Chen, Guican , Zhang, Fujia et al. Clock and data recovery circuit based on DVI [J]. | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors , 2008 , 29 (7) : 1417-1421 .
MLA Xiao, Jian et al. "Clock and data recovery circuit based on DVI" . | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 29 . 7 (2008) : 1417-1421 .
APA Xiao, Jian , Chen, Guican , Zhang, Fujia , Wang, Yongshun . Clock and data recovery circuit based on DVI . | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors , 2008 , 29 (7) , 1417-1421 .
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Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems EI Scopus CSCD
期刊论文 | 2008 , 15 (4) , 107-111 | Journal of China Universities of Posts and Telecommunications
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Abstract :

A fully differential complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) for 3.1-10.6 GHz ultra-wideband (UWB) communication systems is presented. The LNA adopts capacitive cross-coupling common-gate (CG) topology to achieve wideband input matching and low noise figure (NF). Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 μm CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an S11 of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point (IIP3) of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm,a. © 2008 The Journal of China Universities of Posts and Telecommunications.

Keyword :

Capacitive cross-coupling Common gates Complementary metal oxide semiconductors Inductive-series peaking series peaking Ultra wideband communication systems UWB communication system Wideband input matching

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GB/T 7714 ZHANG, Hong , CHEN, Gui-can . Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems [J]. | Journal of China Universities of Posts and Telecommunications , 2008 , 15 (4) : 107-111 .
MLA ZHANG, Hong et al. "Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems" . | Journal of China Universities of Posts and Telecommunications 15 . 4 (2008) : 107-111 .
APA ZHANG, Hong , CHEN, Gui-can . Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems . | Journal of China Universities of Posts and Telecommunications , 2008 , 15 (4) , 107-111 .
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基于DVI的时钟数据恢复电路设计 CSCD PKU
期刊论文 | 2008 , (7) , 1417-1421 | 半导体学报
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设计了一种实现DVI(digital visual interface)数字视频信号接收器的新型时钟数据恢复电路.通过在过采样电路和数字锁相环之间增加弹性缓冲电路,在实现10bit数据恢复的同时,使采样时钟频率减小为数据频率的2.5倍,DPLL同时对10bit并行的数据进行相位检测判断,提高了判断的正确率,使数据传输的误码率得到改善.采用SMIC0.18μm CMOS工艺流片,测试结果表明,输入三路并行的1.65Gbps/ch UXGA格式像素数据和传输电缆长度2m条件下,输出系统时钟信号最大抖动峰.峰值为183ps,均方值为24ps,满足DVI规范要求.

Keyword :

DPLL 时钟数据恢复 过采样 DVI

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GB/T 7714 肖剑 , 陈贵灿 , 张福甲 et al. 基于DVI的时钟数据恢复电路设计 [J]. | 半导体学报 , 2008 , (7) : 1417-1421 .
MLA 肖剑 et al. "基于DVI的时钟数据恢复电路设计" . | 半导体学报 7 (2008) : 1417-1421 .
APA 肖剑 , 陈贵灿 , 张福甲 , 王永顺 . 基于DVI的时钟数据恢复电路设计 . | 半导体学报 , 2008 , (7) , 1417-1421 .
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DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters EI Scopus CSCD PKU
期刊论文 | 2007 , 24 (4) , 480-486 | Jisuan Wuli/Chinese Journal of Computational Physics
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Abstract :

The B3LYP method of density functional theory (DFT) is used to optimize geometry configuration, stability and frequency calculation of GanN+ (n = 2-8) and GanN2+ (n = 1-7) cation clusters at the level of 6-31G*. Ground state of GanN+ (n = 2-8) and GanN2+ (n = 1-7) clusters are obtained. The geometry of clusters transforms from a planar structure to a spacial structure as cluster sizes of GanN+ (n = 2-8) and GanN2+ (n = 1-7) are increased to 6 and 7, respectively. Among GanN+ (n = 2-8) and GanN2+ (n = 1-7) cation clusters, Ga4N+, Ga6N+, Ga3N2+ and Ga5N2+ are more stable.

Keyword :

Clusters Geometry structure Planar structure Spacial structure

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GB/T 7714 Li, Enling , Ma, Hong , Chen, Guican et al. DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters [J]. | Jisuan Wuli/Chinese Journal of Computational Physics , 2007 , 24 (4) : 480-486 .
MLA Li, Enling et al. "DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters" . | Jisuan Wuli/Chinese Journal of Computational Physics 24 . 4 (2007) : 480-486 .
APA Li, Enling , Ma, Hong , Chen, Guican , Wang, Xuewen . DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters . | Jisuan Wuli/Chinese Journal of Computational Physics , 2007 , 24 (4) , 480-486 .
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集成双层平面电感的单片DC/DC转换器设计
期刊论文 | 2007 , (2) , 487-490 | 电子器件
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采用0.35μm标准CMOS工艺设计了3.3V/1.5V单片低压Buck转换器,开关频率为150MHz.本文采用了电压型脉宽调制的反馈控制模式,克服了频率提高所带来的转换器系统不稳定问题.对双层平面螺旋电感进行了设计与优化,获得品质因数2.6,电感值28nH的双层平面电感.模拟结果表明,对应于不同输入电压或不同负载,转换器系统工作稳定,输入调整率-40dB,输出调整率-60dB输出电压纹波平均值可以控制在额定值75mV,转换效率71%.

Keyword :

输出电压纹波 转换效率 双层平面电感器 调整率 单片Buck转换器

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GB/T 7714 李清华 , 邵志标 , 张春茗 et al. 集成双层平面电感的单片DC/DC转换器设计 [J]. | 电子器件 , 2007 , (2) : 487-490 .
MLA 李清华 et al. "集成双层平面电感的单片DC/DC转换器设计" . | 电子器件 2 (2007) : 487-490 .
APA 李清华 , 邵志标 , 张春茗 , 耿莉 . 集成双层平面电感的单片DC/DC转换器设计 . | 电子器件 , 2007 , (2) , 487-490 .
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从头计算对GanNm团簇的结构与稳定性的研究 CSCD PKU
期刊论文 | 2007 , (3) , 477-485 | 原子与分子物理学报
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用B3LYP-DFT方法对GanN2(n=1~7)和GanN(n=2~8)团簇的结构与稳定性进行了研究.在6-31G*水平上进行了结构优化和频率分析,得到了GanN2(n=1~7)和GanN(n=2~8)团簇的基态结构.在GanN(n=2~8)团簇的基态几何结构中,N原子处在分子结构的中心;在GanN2(n=1~3)团簇中,N-N键比Ga-N键强;在GanN2(n=4~7)团簇中存在Ga3N单元和Ga4N单元.在GanN2(n=1~7)和GanN(n=2~8)团簇中,Ga4N2,Ga6P2,Ga3N,Ga5N和Ga7N较其它团簇稳定.

Keyword :

结构 密度泛函理论(DFT) GanNm团簇 稳定性

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GB/T 7714 李恩玲 , 陈贵灿 , 王雪文 et al. 从头计算对GanNm团簇的结构与稳定性的研究 [J]. | 原子与分子物理学报 , 2007 , (3) : 477-485 .
MLA 李恩玲 et al. "从头计算对GanNm团簇的结构与稳定性的研究" . | 原子与分子物理学报 3 (2007) : 477-485 .
APA 李恩玲 , 陈贵灿 , 王雪文 , 马德明 , 薛英 , 马红 . 从头计算对GanNm团簇的结构与稳定性的研究 . | 原子与分子物理学报 , 2007 , (3) , 477-485 .
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GanNm+(n=1~8,m=1~2)团簇的结构及稳定性的DFT研究 CSCD PKU
期刊论文 | 2007 , (4) , 480-486 | 计算物理
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用密度泛函理论(DFT)的B3LYP方法在6-31C*水平上对GanN+(n=2~8)和GanN2+(n=1~7)阳离子团簇的几何结构、稳定性和振动频率等进行研究,得到GanN+(n=2~8)和GanN2+(n=1~7)阳离子团簇的基态结构.其中,GanN+(n=2~8)团簇在总原子数≤6时,其几何结构为平面结构,总原子数>6时,其几何结构为立体结构,N原子位于立体结构的中心;GanN2+(n=2~7)团簇在总原子数≤7时,其基态几何结构为平面结构,总原子数>7时,其基态几何结构为立体结构;原子总数为奇数的团簇Ga4N+,Ga6N+,Ga3N2+和Ga5N2+的基态结构较稳定.

Keyword :

密度泛函理论(DFT) 团簇 几何结构 稳定性

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GB/T 7714 李恩玲 , 马红 , 陈贵灿 et al. GanNm+(n=1~8,m=1~2)团簇的结构及稳定性的DFT研究 [J]. | 计算物理 , 2007 , (4) : 480-486 .
MLA 李恩玲 et al. "GanNm+(n=1~8,m=1~2)团簇的结构及稳定性的DFT研究" . | 计算物理 4 (2007) : 480-486 .
APA 李恩玲 , 马红 , 陈贵灿 , 王雪文 . GanNm+(n=1~8,m=1~2)团簇的结构及稳定性的DFT研究 . | 计算物理 , 2007 , (4) , 480-486 .
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