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Abstract :
This study proposes an analytical drain model of the strained junctionless nanowire tunnel field-effect transistor fabricated on the Si1 - xGex virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the Si1 - xGex virtual substrate. An analytical expression for the drain current is derived by using the tangent line approximation method. The strain induced in the device could reduce the effective tunnelling barrier significantly, resulting in a larger band-to-band tunnelling generation rate and, therefore, higher drive current compared with the unstrained device. Impacts of device parameters such as the channel diameter, gate oxide thickness and gate dielectric constant on the device performance are investigated. Results of the proposed model are verified by comparing with the device simulator. © The Institution of Engineering and Technology 2020.
Keyword :
Dielectric materials Drain current Fabrication Gate dielectrics Nanowires Poisson equation Semiconductor alloys Si-Ge alloys Strained silicon Substrates Tunnel field effect transistors
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GB/T 7714 | Zhang, Yefei , Li, Zunchao . Analytical drain current model of strained junctionless nanowire tunnel field-effect transistor fabricated on Si1-xGex virtual substrate [J]. | IET Circuits, Devices and Systems , 2020 , 14 (8) : 1195-1200 . |
MLA | Zhang, Yefei 等. "Analytical drain current model of strained junctionless nanowire tunnel field-effect transistor fabricated on Si1-xGex virtual substrate" . | IET Circuits, Devices and Systems 14 . 8 (2020) : 1195-1200 . |
APA | Zhang, Yefei , Li, Zunchao . Analytical drain current model of strained junctionless nanowire tunnel field-effect transistor fabricated on Si1-xGex virtual substrate . | IET Circuits, Devices and Systems , 2020 , 14 (8) , 1195-1200 . |
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The three kinds of gases such as NO2, NO, and SO2 produced by industrial combustion process are the main sources of atmospheric pollution. Almost all the available technologies of measuring three components in mixed gases are limited by detection range, operating temperature, and integration, etc. Here we report an array with three triple-electrode carbon nanotube sensors and its sensitivity to the three flue gas components. The three sensors operate at the same gas ionization mechanism and are comprised of a common long cathode, three extracting electrodes and three collecting electrodes, and are set by different electrode separations with 75 μm, 100 μm, and 120 μm, respectively. We explored and obtained distinct single-valued sensitive characteristics to the three-component gases at given voltages applied on electrodes, which should be higher than a critical voltage to obtain single-valued sensitivities of the three sensors. The standard deviation of repeatability experiment is less than 0.133 nA, which indicates that the sensor has a good repeatability. The array displays a high level of integration and small size, and also has the potential to detect the concentrations of different components of gas mixtures. © 2019 IEEE.
Keyword :
Carbon nanotubes Electrodes Gases Gas mixtures Industrial electronics Ionization of gases
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GB/T 7714 | Zhang, Yong , Cheng, Zhenzhen , Chen, Qiyu et al. A Carbon Nanotube Based Ionization Sensor Array to Gas Mixture [C] . 2019 : 5433-5438 . |
MLA | Zhang, Yong et al. "A Carbon Nanotube Based Ionization Sensor Array to Gas Mixture" . (2019) : 5433-5438 . |
APA | Zhang, Yong , Cheng, Zhenzhen , Chen, Qiyu , Song, Xu , Ke, Longlong , Zhao, Yu et al. A Carbon Nanotube Based Ionization Sensor Array to Gas Mixture . (2019) : 5433-5438 . |
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Abstract :
This study investigated the resistive switching characteristics of the Ni/HfO2/Pt structure for nonvolatile memory application. The Ni/HfO2/Pt device showed bipolar resistive switching (RS) without a forming process, and the formation and rupture of conducting filaments are responsible for the resistive switching phenomenon. In addition, the device showed some excellent memory performances, including a large on/off ratio (> 3 × 105), very good data retention (> 103 s @ 200 °C) and uniformity of switching parameters. Considering these results, the Ni/HfO2/Pt device has the potential for nonvolatile memory applications. © 2012 Chinese Institute of Electronics.
Keyword :
Conducting filament Conductive filaments Forming process Good data HfO2 Memory performance Non-volatile memory application On/off ratio Programmable metallization cells Resistive random access memory Resistive switching Switching parameters
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GB/T 7714 | Zhang, Xiao . Resistive switching characteristics of Ni/HfO2/Pt ReRAM [J]. | Journal of Semiconductors , 2012 , 33 (5) . |
MLA | Zhang, Xiao . "Resistive switching characteristics of Ni/HfO2/Pt ReRAM" . | Journal of Semiconductors 33 . 5 (2012) . |
APA | Zhang, Xiao . Resistive switching characteristics of Ni/HfO2/Pt ReRAM . | Journal of Semiconductors , 2012 , 33 (5) . |
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Abstract :
A CMOS wideband front-end IC is demonstrated in this paper. It consists of a low noise transconductance amplifier (LNTA) and a direct RF sampling mixer (DSM) with embedded programmable discrete-time filtering. The LNTA has the features of 0.5-6 GHz wideband, wideband input matching and low noise. The embedded filter following the DSM operates in discrete-time charge domain, filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency. The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz. It shows a conversion gain of 12.6 dB and IP1dB of -7.5 dBm at 2.4 GHz. It occupies a chip area of 0.23 mm2 and consumes 14 mA DC current. © 2011 Chinese Institute of Electronics.
Keyword :
Discrete time DSM FIR filtering IIR LNTA Wide-band windowed integration
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GB/T 7714 | Xu, Jiangtao , Saavedra, Carlos E. , Chen, Guican . A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering [J]. | Journal of Semiconductors , 2011 , 32 (8) . |
MLA | Xu, Jiangtao et al. "A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering" . | Journal of Semiconductors 32 . 8 (2011) . |
APA | Xu, Jiangtao , Saavedra, Carlos E. , Chen, Guican . A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering . | Journal of Semiconductors , 2011 , 32 (8) . |
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Abstract :
The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators' decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2. © 2009 The Journal of China Universities of Posts and Telecommunications.
Keyword :
Analog signals Decision levels Digital correction International corporation Pipelined ADCs Pipelined analog-to-digital converter Residue voltage Transition errors
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GB/T 7714 | JIA, Hua-yu , CHEN, Gui-can , ZHANG, Hong . A new structure of substage in pipelined analog-to-digital converters [J]. | Journal of China Universities of Posts and Telecommunications , 2009 , 16 (1) : 86-90 . |
MLA | JIA, Hua-yu et al. "A new structure of substage in pipelined analog-to-digital converters" . | Journal of China Universities of Posts and Telecommunications 16 . 1 (2009) : 86-90 . |
APA | JIA, Hua-yu , CHEN, Gui-can , ZHANG, Hong . A new structure of substage in pipelined analog-to-digital converters . | Journal of China Universities of Posts and Telecommunications , 2009 , 16 (1) , 86-90 . |
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Abstract :
A novel clock and data recovery circuit has been designed to implement a digital visual interface (DVI) receiver. A flexible buffer was placed between the over-sampler and DPLL. Not only was 10 bits data recovery implemented, but also the frequency of sampling clock was reduced to 2.5 times of the data frequency. The phase verification for 10 bit parallel data by DPLL increases the accuracy rate of judgment and improves the bit error rate. The receiver has been fabricated with an SMIC 0.18 μm CMOS process. The testing results show that the maximum peak-peak and RMS jitters of the output system clock are 183 ps and 24 ps, respectively, under the measuring condition that the data rate is 1.65 Gbps/ch for inputting a UXGA pixel data signal with 2 m cable.
Keyword :
Accuracy rate Clock and data recovery Data recovery DPLL Measuring conditions Over-sampler Sampling clocks Visual Interface
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GB/T 7714 | Xiao, Jian , Chen, Guican , Zhang, Fujia et al. Clock and data recovery circuit based on DVI [J]. | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors , 2008 , 29 (7) : 1417-1421 . |
MLA | Xiao, Jian et al. "Clock and data recovery circuit based on DVI" . | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 29 . 7 (2008) : 1417-1421 . |
APA | Xiao, Jian , Chen, Guican , Zhang, Fujia , Wang, Yongshun . Clock and data recovery circuit based on DVI . | Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors , 2008 , 29 (7) , 1417-1421 . |
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Abstract :
设计了一种实现DVI(digital visual interface)数字视频信号接收器的新型时钟数据恢复电路.通过在过采样电路和数字锁相环之间增加弹性缓冲电路,在实现10bit数据恢复的同时,使采样时钟频率减小为数据频率的2.5倍,DPLL同时对10bit并行的数据进行相位检测判断,提高了判断的正确率,使数据传输的误码率得到改善.采用SMIC0.18μm CMOS工艺流片,测试结果表明,输入三路并行的1.65Gbps/ch UXGA格式像素数据和传输电缆长度2m条件下,输出系统时钟信号最大抖动峰.峰值为183ps,均方值为24ps,满足DVI规范要求.
Keyword :
DPLL DVI 过采样 时钟数据恢复
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GB/T 7714 | 肖剑 , 陈贵灿 , 张福甲 et al. 基于DVI的时钟数据恢复电路设计 [J]. | 半导体学报 , 2008 , (7) : 1417-1421 . |
MLA | 肖剑 et al. "基于DVI的时钟数据恢复电路设计" . | 半导体学报 7 (2008) : 1417-1421 . |
APA | 肖剑 , 陈贵灿 , 张福甲 , 王永顺 . 基于DVI的时钟数据恢复电路设计 . | 半导体学报 , 2008 , (7) , 1417-1421 . |
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Abstract :
A fully differential complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) for 3.1-10.6 GHz ultra-wideband (UWB) communication systems is presented. The LNA adopts capacitive cross-coupling common-gate (CG) topology to achieve wideband input matching and low noise figure (NF). Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 μm CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an S11 of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point (IIP3) of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm,a. © 2008 The Journal of China Universities of Posts and Telecommunications.
Keyword :
Capacitive cross-coupling Common gates Complementary metal oxide semiconductors Inductive-series peaking series peaking Ultra wideband communication systems UWB communication system Wideband input matching
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GB/T 7714 | ZHANG, Hong , CHEN, Gui-can . Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems [J]. | Journal of China Universities of Posts and Telecommunications , 2008 , 15 (4) : 107-111 . |
MLA | ZHANG, Hong et al. "Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems" . | Journal of China Universities of Posts and Telecommunications 15 . 4 (2008) : 107-111 . |
APA | ZHANG, Hong , CHEN, Gui-can . Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems . | Journal of China Universities of Posts and Telecommunications , 2008 , 15 (4) , 107-111 . |
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Abstract :
The B3LYP method of density functional theory (DFT) is used to optimize geometry configuration, stability and frequency calculation of GanN+ (n = 2-8) and GanN2+ (n = 1-7) cation clusters at the level of 6-31G*. Ground state of GanN+ (n = 2-8) and GanN2+ (n = 1-7) clusters are obtained. The geometry of clusters transforms from a planar structure to a spacial structure as cluster sizes of GanN+ (n = 2-8) and GanN2+ (n = 1-7) are increased to 6 and 7, respectively. Among GanN+ (n = 2-8) and GanN2+ (n = 1-7) cation clusters, Ga4N+, Ga6N+, Ga3N2+ and Ga5N2+ are more stable.
Keyword :
Clusters Geometry structure Planar structure Spacial structure
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GB/T 7714 | Li, Enling , Ma, Hong , Chen, Guican et al. DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters [J]. | Jisuan Wuli/Chinese Journal of Computational Physics , 2007 , 24 (4) : 480-486 . |
MLA | Li, Enling et al. "DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters" . | Jisuan Wuli/Chinese Journal of Computational Physics 24 . 4 (2007) : 480-486 . |
APA | Li, Enling , Ma, Hong , Chen, Guican , Wang, Xuewen . DFT study on structure and stability of GanNm+ (n = 1-8, m = 1-2) clusters . | Jisuan Wuli/Chinese Journal of Computational Physics , 2007 , 24 (4) , 480-486 . |
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Abstract :
采用0.35μm标准CMOS工艺设计了3.3V/1.5V单片低压Buck转换器,开关频率为150MHz.本文采用了电压型脉宽调制的反馈控制模式,克服了频率提高所带来的转换器系统不稳定问题.对双层平面螺旋电感进行了设计与优化,获得品质因数2.6,电感值28nH的双层平面电感.模拟结果表明,对应于不同输入电压或不同负载,转换器系统工作稳定,输入调整率-40dB,输出调整率-60dB输出电压纹波平均值可以控制在额定值75mV,转换效率71%.
Keyword :
单片Buck转换器 调整率 输出电压纹波 双层平面电感器 转换效率
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GB/T 7714 | 李清华 , 邵志标 , 张春茗 et al. 集成双层平面电感的单片DC/DC转换器设计 [J]. | 电子器件 , 2007 , (2) : 487-490 . |
MLA | 李清华 et al. "集成双层平面电感的单片DC/DC转换器设计" . | 电子器件 2 (2007) : 487-490 . |
APA | 李清华 , 邵志标 , 张春茗 , 耿莉 . 集成双层平面电感的单片DC/DC转换器设计 . | 电子器件 , 2007 , (2) , 487-490 . |
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