According　to　the　need　of　developing　digital　video　processing　technology　and　chip　for　flat　panel　device,　a　designing　scheme　using　innovative　architecture　of　digital　video　post-process　chip　DTV100　and　key　technology　indices　are　presented.　3D　denoise,　deinterlace,　frame　rate　up　and　motion　compensation　desawtooth,　movie　mode　disposal　are　implemented　by　one　high　efficient　SDRAM　controller　in　real　time.　A　hardware　implementing　algorithm　for　video　scaling　based　on　bilinear　interpolation　and　a　3D　adaptive　denoise　algorithm　based　on　motion　detection　and　edge　detection　are　presented.　The　proposed　scheme　has　the　characteristics　of　simple　architecture,　saving　hardware　resources　and　steady　performance.　Following　the　normative　chip　design　flow,　the　digital　video　processing　chip　is　implemented　by　application　specific　integrated　circuit　using　0.25　μm　CMOS　technology.　Comparison　with　similar　chips　shows　that　the　chip　is　low　cost.　Function　tests　of　3D　denoise　with　different　denoise　factor　show　that　the　chip　has　normal　function　and　attains　the　expected　technology　indices.