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Abstract:
This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced functions for image quality improvement, including edge-directed image upscaling, guided image filter (GIF) based detail enhancement and noise reduction, multi-view autostereoscopic 3D processing, etc. By leveraging algorithm and architecture co-design, this work efficiently implements these computational intensive display processing functions in a single chip. The chip is fabricated in GF 55nm CMOS technology, and the core size is 38.71mm2 including 1.8M logic gates and 541KB SRAM. The chip works at the maximum operating frequency of 594MHz with the core supply voltage of 1.2V. The maximum input and output video formats reach up to 4Kx2K@60fps.
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2018 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2018)
Year: 2018
Page: 427-430
Language: English
Cited Count:
WoS CC Cited Count: 2
SCOPUS Cited Count:
ESI Highly Cited Papers on the List: 0 Unfold All
WanFang Cited Count:
Chinese Cited Count:
30 Days PV: 2
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