The　three　dimensional　(3D)　integration　technology　using　planar　inductor　as　a　substrate　for　power　converter　is　a　promising　method　to　improve　the　power　density.　But　it　introduces　additional　parasitic　inductance,　not　good　for　the　application　of　GaN　semiconductor　devices.　So　a　conductive　shield　layer　was　introduced　between　the　magnetic　substrate　and　GaN-based　12V/3.3V　synchronous　buck　converter　circuit　to　reduce　loop　inductance.　Based　on　the　selected　split　capacitors　layout　of　power　loop　for　3D　integration,　the　effects　of　shield　layer　thickness　and　insulator　thickness　on　parasitic　inductance　were　investigated　and　optimized.　The　comparison　of　eight　cases　shows　that　3D　integrated　split-capacitors　layout　with　shied　layer　can　realize　the　parasitic　loop　inductance　of　0.26nH　at　inductor　current　of　10A,　which　is　much　smaller　than　0.89nH　of　conventional　lateral　layout　in　2D　integration　structure.　At　last,　considering　all　the　power　losses,　thermal　analyses　were　performed　on　the　3D　integrated　split-capacitors　layout　with　shield,　3D　integrated　split-capacitors　layout　without　shield　and　2D　integrated　split-capacitors　layout　with　shield.　The　results　demonstrate　the　effectiveness　of　shield　on　heat　dissipation,　and　an　acceptable　operating　temperature　of　proposed　3D　integrated　module　was　obtained.　Thus　the　feasibility　of　3D　integrated　structure　using　planar　inductor　as　a　substrate　for　power　converter　is　verified.　©　2018　IEEE.