This　article　presents　a　1st-order　noise-shaping　(NS)　successive　approximation　register　(SAR)　analog-to-digital　converter　(ADC)　with　a　hybrid　error-feedback　(EF)　and　cascaded-integrator-feed-forward　(CIFF)　structure　assisted　by　a　unity-gain　buffer　(UGB).　Without　using　a　multi-input　comparator　which　is　widely　adopted　in　conventional　1st-order　passive　NS　structures,　the　proposed　hybrid　EF-CIFF　structure　realizes　a　more　ideal　1st-order　noise　transfer　function　(NTF)　with　a　reasonable　capacitance　ratio,　so　as　to　obtain　better　NS　effect.　Fabricated　in　a　28-nm　CMOS　technology,　the　prototype　NS-SAR　ADC　consumes　150　mu　W　under　a　0.9-V　supply　voltage　when　operating　at　40-MS/s　sampling　rate.　A　75-dB　signal-to-noise-and-distortion　ratio　(SNDR)　is　measured　for　a　2.47-MHz　sinusoid　input　under　an　oversampling　ratio　(OSR)　of　8.　It　achieves　a　peak　Schreier　figure-of-merit　(FoM)　of　177.2　dB　and　the　core　circuit　occupies　0.012-mm(2)　area.