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Author:

Wei, Sufen (Wei, Sufen.) | Zhang, Guohe (Zhang, Guohe.) | Geng, Li (Geng, Li.) | Shao, Zhibiao (Shao, Zhibiao.) | Yang, Cheng-Fu (Yang, Cheng-Fu.)

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Abstract:

In this paper, we present two silicon-on-insulator tunnel field-effect transistors (SOI-TFETs), referred as a lateral dual-gate TFET and a lateral triple-gate TFET, which consist of one or two vertical thin vertical dielectric layers within the original front-gate region and form the separate dual-gate or triple-gate structure. Using calibrated two-dimensional Synopsys Sentaurus TCAD simulation, we demonstrate that the proposed novel TFETs have relatively higher Ion and significantly lower Ioff due to the modulating effect of the multiple gate voltages on the channel barrier. We also compare and analyze improvements in Ion/Ioff for the two novel SOI-TFETs and a conventional SOI-TFET. The proposed new TFETs exhibit a high Ion/Ioff ratio of 104 ~ 108 for a channel length of 22 nm. Our results reveal that the performance of the lateral triple-gate TFET is superior to that of the dual-gate TFET, yielding higher on-state current and lower off-state current. © 2018, Springer-Verlag GmbH Germany, part of Springer Nature.

Keyword:

Band to band tunneling Compare and analyze Modulating effect Off-state current On state current Performance improvements Tunnel field-effect transistors (TFET) Tunneling barrier

Author Community:

  • [ 1 ] [Wei, Sufen;Zhang, Guohe;Geng, Li;Shao, Zhibiao]School of Microelectronics, Xi’an Jiaotong University, Shaanxi; 710049, China
  • [ 2 ] [Yang, Cheng-Fu]Department of Chemical and Materials Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Rd, Nan-Tzu District, Kaohsiung; 811, Taiwan
  • [ 3 ] [Wei, Sufen]School of Information and Engineering, Jimei University, Fujian; 361021, China
  • [ 4 ] [Wei, Sufen]Xi An Jiao Tong Univ, Sch Microelect, Xian 710049, Shaanxi, Peoples R China
  • [ 5 ] [Zhang, Guohe]Xi An Jiao Tong Univ, Sch Microelect, Xian 710049, Shaanxi, Peoples R China
  • [ 6 ] [Geng, Li]Xi An Jiao Tong Univ, Sch Microelect, Xian 710049, Shaanxi, Peoples R China
  • [ 7 ] [Shao, Zhibiao]Xi An Jiao Tong Univ, Sch Microelect, Xian 710049, Shaanxi, Peoples R China
  • [ 8 ] [Yang, Cheng-Fu]Natl Univ Kaohsiung, Dept Chem & Mat Engn, 700 Kaohsiung Univ Rd, Kaohsiung 811, Taiwan
  • [ 9 ] [Wei, Sufen]Jimei Univ, Sch Informat & Engn, Xiamen 361021, Fujian, Peoples R China

Reprint Author's Address:

  • [Shao, Zhibiao]School of Microelectronics, Xi’an Jiaotong University, Shaanxi; 710049, China;;

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Source :

Microsystem Technologies

ISSN: 0946-7076

Year: 2021

Issue: 4

Volume: 27

Page: 1031-1038

2 . 2 7 6

JCR@2020

ESI Discipline: MATERIALS SCIENCE;

ESI HC Threshold:36

JCR Journal Grade:2

CAS Journal Grade:4

Cited Count:

WoS CC Cited Count: 3

SCOPUS Cited Count: 2

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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