Solving　a　super-high　dimensional　equations　group　is　widely　used　in　science　and　engineering,　but　the　slow　solution　speed　is　the　biggest　problem　researchers　face.　Research　on　FPGA　based　evolvable　hardware　chips　for　solving　the　super-high　dimensional　equations　group　(SHDESC)　is　proposed　in　this　paper.　These　chips　can　be　implemented　on　a　milliongate　scale　FPGA　chip.　The　core　architecture　of　SHDESC　is　a　systolic　array　which　consists　of　thousands　of　special　arithmetic　units　and　can　execute　many　super-high　dimensional　matrix　operations　parallelly　in　short　time　as　well　as　really　achieve　the　purpose　of　high　speed　solution　in　hardware/software　codesign.　The　experiments　show　that　these　chips　can　achieve　high　precision　results　in　a　short　period　of　time　to　solve　a　super-high　dimensional　equations　group.