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Abstract:
An accurate and low-cost technique is proposed for sinusoidal jitter and random jitter estimation in high-speed ADC test. Exploiting the fact that clock jitter is modulated by the slope of input signal, the proposed method can simultaneously extract both information for sinusoidal jitter and random jitter with a single high frequency test. The proposed method is computationally efficient since only one FFT, one IFFT and few simple arithmetic operations are involved. Compared with existing dual-frequency tests and single-frequency tests, both hardware overhead and data acquisition time are saved significantly. Theoretical analysis and simulation results validate the computational efficiency and test accuracy.
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Source :
IEICE ELECTRONICS EXPRESS
ISSN: 1349-2543
Year: 2015
Issue: 20
Volume: 12
0 . 3 4 4
JCR@2015
0 . 5 7 8
JCR@2020
ESI Discipline: ENGINEERING;
ESI HC Threshold:138
JCR Journal Grade:4
CAS Journal Grade:4
Cited Count:
WoS CC Cited Count: 0
SCOPUS Cited Count: 1
ESI Highly Cited Papers on the List: 0 Unfold All
WanFang Cited Count:
Chinese Cited Count:
30 Days PV: 8
Affiliated Colleges: