An　accurate　and　low-cost　technique　is　proposed　for　sinusoidal　jitter　and　random　jitter　estimation　in　high-speed　ADC　test.　Exploiting　the　fact　that　clock　jitter　is　modulated　by　the　slope　of　input　signal,　the　proposed　method　can　simultaneously　extract　both　information　for　sinusoidal　jitter　and　random　jitter　with　a　single　high　frequency　test.　The　proposed　method　is　computationally　efficient　since　only　one　FFT,　one　IFFT　and　few　simple　arithmetic　operations　are　involved.　Compared　with　existing　dual-frequency　tests　and　single-frequency　tests,　both　hardware　overhead　and　data　acquisition　time　are　saved　significantly.　Theoretical　analysis　and　simulation　results　validate　the　computational　efficiency　and　test　accuracy.