Display　frame　compression　is　an　effective　technique　to　address　the　challenge　of　external　memory　access　in　ultrahigh　definition　video　display　system.　Nevertheless,　previously　proposed　display　frame　compression　designs　are　inadequate　in　terms　of　either　energy　efficiency　or　throughput.　This　paper　aims　to　exploit　the　algorithm　and　very　large　scale　integration　(VLSI)　architecture　of　a　worst　case　driven　display　frame　compression.　By　using　a　prediction-and-compression　framework　and　a　semi-fixed　length　coding　scheme,　the　proposed　design　can　achieve　the　much　better　balance　between　compression　efficiency　and　throughput,　and　substantially　reduce　the　bandwidth　requirement　and　energy　consumption　of　external　memory　system　in　the　meanwhile.　Extensive　experiments　demonstrate　that　the　proposed　display　frame　compression　achieves　5.7-dB　peak　signal-to-noise　ratio　improvement,　3.1%　compression　ratio　reduction,　3　x　throughput,　and　66.4%　hardware　cost　saving,　compared　with　the　best　previous　work.　In　addition,　the　proposed　VLSI　design　can　support　the　throughput　of　4　K　x　2　K@60　Hz　and　reduce　at　least　17.6%　energy　consumption　of　external　memory　system　by　exploiting　dynamic　voltage　and　frequency　scaling,　compared　with　conventional　display　frame　compression　works.