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VLSI Architecture Exploration of Guided Image Filtering for 1080P@60Hz Video Processing SCIE
期刊论文 | 2018 , 28 (1) , 230-241 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
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Abstract :

Guided image filtering (GIF) is a promising edge-preserving filtering technique that has been applied in a variety of applications. Nevertheless, an efficient very-large-scale integration (VLSI) architecture design of GIF is still very challenging for the real-time processing of full-high definition videos. Previously proposed architectures are somewhat inefficient in terms of either on-chip memory usage or off-chip memory bandwidth. This paper aims to improve the balance between on-chip memory usage and off-chip memory bandwidth through architecture exploration. Three critical architectural tradeoffs in the VLSI design of GIF are explored, and two efficient VLSI architectures, namely sequential line-based and parallel line-based architectures, are proposed. Experimental results demonstrate that the proposed VLSI design only consumes 34.1-K logic gates, 25.4-KB on-chip memories, and 373-MB/s off-chip memory bandwidth while achieving a real-time video processing of 1080P@60Hz at the maximum clock frequency of 297-MHz. Moreover, the proposed VLSI circuits are fully pipelined and synchronized to the pixel clock of output video, so can be seamlessly integrated into diverse real-time video processing systems.

Keyword :

very-large-scale integration (VLSI) architecture memory hierarchy video processing Guided image filtering (GIF)

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GB/T 7714 Zhang, Xuchong , Sun, Hongbin , Chen, Shiqiang et al. VLSI Architecture Exploration of Guided Image Filtering for 1080P@60Hz Video Processing [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY , 2018 , 28 (1) : 230-241 .
MLA Zhang, Xuchong et al. "VLSI Architecture Exploration of Guided Image Filtering for 1080P@60Hz Video Processing" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 28 . 1 (2018) : 230-241 .
APA Zhang, Xuchong , Sun, Hongbin , Chen, Shiqiang , Zheng, Nanning . VLSI Architecture Exploration of Guided Image Filtering for 1080P@60Hz Video Processing . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY , 2018 , 28 (1) , 230-241 .
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Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing EI SCIE Scopus
期刊论文 | 2018 , 20 (5) , 1113-1125 | IEEE TRANSACTIONS ON MULTIMEDIA
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Abstract :

Display frame compression is an effective technique to address the challenge of external memory access in ultrahigh definition video display system. Nevertheless, previously proposed display frame compression designs are inadequate in terms of either energy efficiency or throughput. This paper aims to exploit the algorithm and very large scale integration (VLSI) architecture of a worst case driven display frame compression. By using a prediction-and-compression framework and a semi-fixed length coding scheme, the proposed design can achieve the much better balance between compression efficiency and throughput, and substantially reduce the bandwidth requirement and energy consumption of external memory system in the meanwhile. Extensive experiments demonstrate that the proposed display frame compression achieves 5.7-dB peak signal-to-noise ratio improvement, 3.1% compression ratio reduction, 3 x throughput, and 66.4% hardware cost saving, compared with the best previous work. In addition, the proposed VLSI design can support the throughput of 4 K x 2 K@60 Hz and reduce at least 17.6% energy consumption of external memory system by exploiting dynamic voltage and frequency scaling, compared with conventional display frame compression works.

Keyword :

memory bandwidth Display frame compression energy efficiency ultra-high definition (HD) video very large scale integration (VLSI) architecture

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GB/T 7714 Chen, Qiubo , Sun, Hongbin , Zheng, Nanning . Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing [J]. | IEEE TRANSACTIONS ON MULTIMEDIA , 2018 , 20 (5) : 1113-1125 .
MLA Chen, Qiubo et al. "Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing" . | IEEE TRANSACTIONS ON MULTIMEDIA 20 . 5 (2018) : 1113-1125 .
APA Chen, Qiubo , Sun, Hongbin , Zheng, Nanning . Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing . | IEEE TRANSACTIONS ON MULTIMEDIA , 2018 , 20 (5) , 1113-1125 .
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Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction EI SCIE Scopus
期刊论文 | 2017 , 66 (5) , 820-833 | IEEE TRANSACTIONS ON COMPUTERS | IF: 3.052
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Abstract :

Although the emerging 3D DRAM products can significantly improve the computing system performance, the relatively high cost is one of the most critical issues that prevent their wide real-life adoption. Intuitively, a strong memory fault tolerance can be leveraged to reduce the fabrication cost of DRAM dies, and the total cost will reduce if the fabrication cost saving can off-set the cost overhead of memory fault tolerance. Nevertheless, such a simple concept can be a practically viable option only for 3D DRAM because: (1) The stacked logic die can solely implement memory fault tolerance inside 3D DRAM chips, obviating any changes on the host CPUs and CPU-DRAM interfaces. (2) With the total ownership of both the logic die and DRAM dies inside 3D DRAM chips, DRAM manufacturers can fully exploit the potential to truly minimize the 3D DRAM bit cost. Following this intuition, we developed a 3D DRAM fault tolerance design strategy. It can achieve a very strong tolerance to weak DRAM cells at very small redundancy and latency overhead. The key is to cohesively leverage the detectability of weak cells and runtime configurability of error correction code (ECC) decoding. In addition, this design strategy can gracefully embrace the inaccuracy of weak cell detection (e. g., weak cell miss-detection and false-detection). We carried out thorough mathematical analysis, and the results show that, under the redundancy overhead of 1: 8 (same as today's ECC DIMM), this design strategy can tolerate the weak cell rate of as high as 10(-4) and 6 x 10(-5) if 100 and 90 percent of all the weak cells are known in prior. Using Micron's hybrid memory cube (HMC) 3D DRAM chips as the test vehicle, we evaluated the implementation cost and the results show that it only consumes less than 0.4 mm(2) (45 nm node) on the logic die. Using CPU and DRAM simulators, we further carried out simulations over a variety of computing benchmarks and the results show that this design solution only incurs less than 2 percent performance degradation on average.

Keyword :

DRAM 3D integration Memory fault tolerance error correction code (ECC)

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GB/T 7714 Wang, Hao , Zhao, Kai , Lv, Minjie et al. Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction [J]. | IEEE TRANSACTIONS ON COMPUTERS , 2017 , 66 (5) : 820-833 .
MLA Wang, Hao et al. "Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction" . | IEEE TRANSACTIONS ON COMPUTERS 66 . 5 (2017) : 820-833 .
APA Wang, Hao , Zhao, Kai , Lv, Minjie , Zhang, Xuebin , Sun, Hongbin , Zhang, Tong . Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction . | IEEE TRANSACTIONS ON COMPUTERS , 2017 , 66 (5) , 820-833 .
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sWMF: Separable Weighted Median Filter for Efficient Large-Disparity Stereo Matching EI CPCI-S Scopus
会议论文 | 2017 , 1922-1925 | IEEE International Symposium on Circuits and Systems (ISCAS)
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Abstract :

Although large disparity stereo matching is critical to the practical application of stereo vision system especially for outdoor scenes, its efficient hardware design is still a grand challenge. Motivated by the discovery that well-designed weighted median filter (WMF) can achieve satisfactory accuracy with simple box-filter aggregation, this paper proposes a separable weighted median filter (sWMF) that only has the computational complexity of O(r) and is independent of disparity range. Moreover, the proposed sWMF can be efficiently implemented as a fully pipelined architecture. Evaluation results demonstrate that, at the penalty of only 0.06% disparity error rate, the proposed sWMF design can save 12.9% Slice LUTs, 76.7% DSPs and 64.0% Block RAMs at the disparity range of 128, compared with previous WMF implementation on FPGA.

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GB/T 7714 Chen, Shiqiang , Zhang, Xuchong , Sun, Hongbin et al. sWMF: Separable Weighted Median Filter for Efficient Large-Disparity Stereo Matching [C] . 2017 : 1922-1925 .
MLA Chen, Shiqiang et al. "sWMF: Separable Weighted Median Filter for Efficient Large-Disparity Stereo Matching" . (2017) : 1922-1925 .
APA Chen, Shiqiang , Zhang, Xuchong , Sun, Hongbin , Zheng, Nanning . sWMF: Separable Weighted Median Filter for Efficient Large-Disparity Stereo Matching . (2017) : 1922-1925 .
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Zynq-based Full HD Around View Monitor System for Intelligent Vehicle EI CPCI-S Scopus
会议论文 | 2017 , 1079-1082 | 9th Annual Summit and Conference of the Asia-Pacific-Signal-and-Information-Processing-Association (APSIPA ASC)
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Abstract :

Around View Monitoring (AVM) system is a computer vision application in advanced driver-assistance systems (ADASs). When using full high-definition (HD) camera, it brings significant challenge to system design. Multi-channel HI) cameras bring great pressure to video processing system, especially the communication between the processing circuit and memory. To address these issues, this paper proposes a software-hardware codesigned AVM system. In particular, we present and implement a computational efficient composing algorithm for high quality bird's-eye view image and a cost efficient hardware architecture for low memory bandwidth. The performance of the proposed full HI) AVM system can reach up to 30 frames per second.

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GB/T 7714 Lai, Cong , Luo, Wen , Chen, Shiqiang et al. Zynq-based Full HD Around View Monitor System for Intelligent Vehicle [C] . 2017 : 1079-1082 .
MLA Lai, Cong et al. "Zynq-based Full HD Around View Monitor System for Intelligent Vehicle" . (2017) : 1079-1082 .
APA Lai, Cong , Luo, Wen , Chen, Shiqiang , Li, Qinhua , Yang, Qingyu , Sun, Hongbin et al. Zynq-based Full HD Around View Monitor System for Intelligent Vehicle . (2017) : 1079-1082 .
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On the Use of DRAM with Unrepaired Weak Cells in Computing Systems EI CPCI-S Scopus
会议论文 | 2016 , 327-337 | International Symposium on Memory Systems (MEMSYS)
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Abstract :

In current practice, DRAM manufacturers apply redundancy repair to decommission all the weak cells that cannot satisfy the target data retention time under the worse-case operational conditions (e.g., the highest operating temperature). However, as the DRAM scaling enters sub-20nm regime, it becomes increasingly challenging to repair all the weak cells at reasonable cost. This work studies how one could use DRAM chips with unrepaired weak cells in computing systems. In particular, this work is based upon the simple idea that OS reserves all the error-prone pages, which contain at least one unrepaired weak cell, from being used. Under a relatively high error-prone page rate (e.g., 8%), this basic idea is subject to two issues: (1) Simply reserving all the error prone pages could make it almost impossible for OS to allocate a continuous fragmentation-free physical memory space for some critical operations such as OS booting and DMA buffering. (2) Since most error-prone pages may only contain few unrepaired weak cells, reserving all the error-prone pages from practical usage could cause noticeable memory resource waste. Aiming to address these issues, this paper presents a controller-based selective page re-mapping strategy to ensure a continuous critical memory region for OS, and develops a software-based memory error tolerance scheme to re-cycle all the error-prone pages for the zRAM function in Linux. Since the first scheme only eliminates the fragmentation in the critical memory region (e.g., 128MB in Linux), the remaining non-critical memory region is still subject to severe fragmentation. Hence, we carried out experiments using SPEC CPU2006 to quantitatively demonstrate that highly fragmented non-critical memory region may not cause significant computing system performance degradation. We further study the latency and hardware cost of implementing the controller-based page re-mapping, and the effectiveness of re-cycling error-prone pages for zRAM in Linux. The experimental results show that our proposed software-based error tolerance scheme degrades the speed performance of zRAM by only up to 7%.

Keyword :

Error Tolerance DRAM Compression zRAM

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GB/T 7714 Wang, Hao , Li, Yin , Zhang, Xuebin et al. On the Use of DRAM with Unrepaired Weak Cells in Computing Systems [C] . 2016 : 327-337 .
MLA Wang, Hao et al. "On the Use of DRAM with Unrepaired Weak Cells in Computing Systems" . (2016) : 327-337 .
APA Wang, Hao , Li, Yin , Zhang, Xuebin , Zhao, Xiaoqing , Sun, Hongbin , Zhang, Tong . On the Use of DRAM with Unrepaired Weak Cells in Computing Systems . (2016) : 327-337 .
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Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud EI CPCI-S Scopus
会议论文 | 2016 , 268-278 | International Symposium on Memory Systems (MEMSYS)
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Abstract :

With the nature of being memory hungry, in-memory key-value store is fundamentally subject to very high memory cost and energy consumption. Intuitively, the availability of a strong memory error correction at sufficiently small redundancy overhead could be leveraged to reduce memory cost and/or energy consumption. Nevertheless, current computing systems handle memory error correction solely in the hardware stack with very weak error correction strength. This paper for the first time studies the practical feasibility of implementing strong memory error correction code (ECC) in the software stack for in-memory key-value store without incurring significant speed performance penalty. This is fundamentally enabled by the low memory bandwidth utilization and relatively simple data structure of in-memory key-value store, which are actually shared with many other datacenter applications (e.g., Web search). This paper presents several design techniques to optimize software-based ECC implementation for in-memory key-value store, and elaborates on several important design issues. Using Memcached and RAMCloud as test vehicles, this work shows that the proposed design solution can improve the memory error correction strength by several orders of magnitude at similar (and even less) coding redundancy compared with current hardware-based design practice, and meanwhile incur less than 6% degradation of in-memory key-value store operational throughput.

Keyword :

Error Correction In-memory Key-value Store Memory Fault Tolerance

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GB/T 7714 Li, Yin , Wang, Hao , Zhao, Xiaoqing et al. Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud [C] . 2016 : 268-278 .
MLA Li, Yin et al. "Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud" . (2016) : 268-278 .
APA Li, Yin , Wang, Hao , Zhao, Xiaoqing , Sun, Hongbin , Zhang, Tong . Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud . (2016) : 268-278 .
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RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters EI SCIE Scopus
期刊论文 | 2016 , 72 (1) , 295-316 | JOURNAL OF SUPERCOMPUTING | IF: 1.326
WoS CC Cited Count: 4
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Abstract :

Datacenters, the essential infrastructures for supercomputing and cloud computing, are facing increasing pressure of capping tremendous power consumption and carbon emission. Many studies have proposed to leverage energy storage devices to shave peak power or smooth intermittent power for datacenters, respectively. However, a joint energy management of peak shaving and renewable energy harvesting in datacenters is still lacking. In this paper, we propose a new power management scheme named RE-UPS, which explores the opportunity to shave datacenter peak power demand with renewable energy. RE-UPS is based on the emerging distributed energy storage architecture and existing UPS infrastructure of datacenter. It further leverages a dynamic heuristic algorithm to determine the appropriate energy storage allocation and server power sources. The proposed energy management policies can greatly optimize the design among maximizing renewable energy harvest, shaving peak power, and maintaining UPS energy availability. Compared to the baseline power management schemes, RE-UPS can averagely improve backup energy capacity by 28 %, extend battery lifetime by 42 %, increase green energy utilization by 78 %, and reduce workload performance degradation by 13 %.

Keyword :

Power management Datacenter Renewable energy Availability Sustainability Energy storage UPS

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GB/T 7714 Liu, Longjun , Sun, Hongbin , Li, Chao et al. RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters [J]. | JOURNAL OF SUPERCOMPUTING , 2016 , 72 (1) : 295-316 .
MLA Liu, Longjun et al. "RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters" . | JOURNAL OF SUPERCOMPUTING 72 . 1 (2016) : 295-316 .
APA Liu, Longjun , Sun, Hongbin , Li, Chao , Hu, Yang , Xin, Jingmin , Zheng, Nanning et al. RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters . | JOURNAL OF SUPERCOMPUTING , 2016 , 72 (1) , 295-316 .
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On-Road Vehicle Detection and Tracking Using MMW Radar and Monovision Fusion EI SCIE Scopus
期刊论文 | 2016 , 17 (7) , 2075-2084 | IEEE TRANSACTIONS ON INTELLIGENT TRANSPORTATION SYSTEMS | IF: 3.724
WoS CC Cited Count: 9
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Abstract :

With the potential to increase road safety and provide economic benefits, intelligent vehicles have elicited a significant amount of interest from both academics and industry. A robust and reliable vehicle detection and tracking system is one of the key modules for intelligent vehicles to perceive the surrounding environment. The millimeter-wave radar and the monocular camera are two vehicular sensors commonly used for vehicle detection and tracking. Despite their advantages, the drawbacks of these two sensors make them insufficient when used separately. Thus, the fusion of these two sensors is considered as an efficient way to address the challenge. This paper presents a collaborative fusion approach to achieve the optimal balance between vehicle detection accuracy and computational efficiency. The proposed vehicle detection and tracking design is extensively evaluated with a real-world data set collected by the developed intelligent vehicle. Experimental results show that the proposed system can detect on-road vehicles with 92.36% detection rate and 0% false alarm rate, and it only takes ten frames (0.16 s) for the detection and tracking of each vehicle. This systemis installed on Kuafu-II intelligent vehicle for the fourth and fifth autonomous vehicle competitions, which is called "Intelligent Vehicle Future Challenge" in China.

Keyword :

MMW radar sensor fusion Intelligent vehicle monocular camera vehicle detection and tracking

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GB/T 7714 Wang, Xiao , Xu, Linhai , Sun, Hongbin et al. On-Road Vehicle Detection and Tracking Using MMW Radar and Monovision Fusion [J]. | IEEE TRANSACTIONS ON INTELLIGENT TRANSPORTATION SYSTEMS , 2016 , 17 (7) : 2075-2084 .
MLA Wang, Xiao et al. "On-Road Vehicle Detection and Tracking Using MMW Radar and Monovision Fusion" . | IEEE TRANSACTIONS ON INTELLIGENT TRANSPORTATION SYSTEMS 17 . 7 (2016) : 2075-2084 .
APA Wang, Xiao , Xu, Linhai , Sun, Hongbin , Xin, Jingmin , Zheng, Nanning . On-Road Vehicle Detection and Tracking Using MMW Radar and Monovision Fusion . | IEEE TRANSACTIONS ON INTELLIGENT TRANSPORTATION SYSTEMS , 2016 , 17 (7) , 2075-2084 .
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Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device EI SCIE Scopus
期刊论文 | 2016 , 24 (8) , 2654-2664 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | IF: 1.698
WoS CC Cited Count: 6
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Abstract :

A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and the soft-decision memory sensing become indispensable in the next-generation flash-based solid-state storage devices. However, the use of LDPC codes inevitably increases memory read latency and, hence, degrades speed performance. Motivated by the observation of intracell unbalanced bit error probability and data dependence in the MLC NAND flash memory, this paper proposes two techniques, i.e., intracell data placement interleaving and intracell data dependence aware LDPC decoding, to efficiently improve the LDPC decoding throughput and energy efficiency for the MLC NAND flash-based storage in a mobile device. Experimental results show that, by exploiting the intracell bit-error characteristics, the proposed techniques together can improve the LDPC decoding throughput by up to 84.6% and reduce the energy consumption by up to 33.2% while only incurring less than 0.2% silicon area overhead.

Keyword :

Bit-error characteristic multilevel per cell (MLC) NAND flash solid-state storage low-density parity-check (LDPC) codes

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GB/T 7714 Sun, Hongbin , Zhao, Wenzhe , Lv, Minjie et al. Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device [J]. | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 2016 , 24 (8) : 2654-2664 .
MLA Sun, Hongbin et al. "Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device" . | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24 . 8 (2016) : 2654-2664 .
APA Sun, Hongbin , Zhao, Wenzhe , Lv, Minjie , Dong, Guiqiang , Zheng, Nanning , Zhang, Tong . Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device . | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 2016 , 24 (8) , 2654-2664 .
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