Efficient　transaction　nesting　is　one　of　the　ongoing　challenges　for　hardware　transactional　memory.　To　increase　efficiency　of　closed　nesting,　this　paper　proposes　a　conditional　partial　rollback　(CPR)　scheme　which　supports　conditional　partial　rollback　without　increasing　hardware　complexities　significantly.　In　stead　of　rolling　back　to　the　outermost　transaction　as　in　commonly-used　flattening　model,　the　CPR　scheme　just　rolls　back　to　the　conflicted　transaction　itself　or　one　of　its　outer-level　transactions　if　given　conditions　are　satisfied.　By　recording　access　status　of　each　nested　transaction,　the　scheme　uses　one　global　data　set　for　all　of　the　nested　transactions　rather　than　independent　data　set　for　each　nested　transaction.　Hardware　transactional　memory　architecture　with　Hie　support　of　CPR　scheme　is　also　proposed　based　on　multi-core　processor　and　current　cache　coherence　mechanism.　Time　system　is　implemented　by　simulation,　and　evaluated　using　seven　benchmark　applications.　Evaluation　results　show　that　the　CPR　scheme　achieves　better　performance　and　scalability　than　the　flattening　model　which　is　commonly-used　in　hardware　transactional　memory.