In　the　single-phase　voltage　source　inverter　(VSI),　the　instantaneous　output　power　pulsates　at　twice　the　line　frequency,　generating　second-harmonic　voltage　in　dc　bus.　Bulky　electrolytic　capacitors　or　additional　auxiliary　circuits　are　used　in　traditional　methods,　which　inevitably　limit　the　system　lifetime,　efficiency,　and　power　density.　In　this　article,　the　input-parallel　output-series　(IPOS)　dual　active　bridge　(DAB)　with　differentiated-capacitance　design　is　adopted　as　the　front-end　dc-dc　stage.　The　pulsating　power　is　compensated　by　the　energy　gap　that　the　differentiated　output　capacitors　release.　The　small-signal　model　of　the　IPOS　DAB　fed　VSI　is　built,　and　based　on　which,　the　voltage-complementary　algorithm　is　proposed.　Then,　the　preferred　zone　and　optimization　scheme　of　the　main　circuit　parameters　are　designed　according　to　the　quantitative　analysis　of　the　suppressing　effect.　Furthermore,　a　625-W　IPOS　DAB　fed　VSI　design　example　is　presented　and　tested.　The　experimental　result　shows　that　at　least　seven　times　the　capacitance　requirements　can　be　reduced　without　any　additional　components,　and　the　power　quality　of　both　the　input　current　and　the　output　voltage　is　well　guaranteed.　©　1986-2012　IEEE.