Indexed by：
Abstract：
This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2nd-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM. © 2018 IEEE.
Keyword：
Reprint Author's Address：
Email：
Source ：
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ISSN： 9781538667002
Year： 2018
Publish Date： October 22, 2018
Volume： 2018-June
Page： 203-204
Language： English
Cited Count：
WoS CC Cited Count： 0
SCOPUS Cited Count： 18
ESI Highly Cited Papers on the List： 0 Unfold All
WanFang Cited Count：
Chinese Cited Count：
30 Days PV： 2
Affiliated Colleges：
