Accurate　nonlinear　parasitic　capacitance　characterization　of　silicon　carbide　(SiC)　metal-oxide-semiconductor　field-effect　transistor　(MOSFETs)　is　essential　for　device　behavior　modeling,　circuit　switching　loss　optimization　and　power　electronic　equipment　design.　This　paper　presents　an　improved　characterization　method　of　drain-source　capacitance　Cds　for　SiC　MOSFET,　which　combines　parasitic　capacitance　extraction　in　dynamic　switching　process　and　static　segmented　capacitance　characterization.　Firstly,　an　extraction　method　of　parasitic　capacitance　during　dynamic　switching　transient　based　on　miller　plateau　is　described　and　it　can　reflect　the　real　value　of　Cds　in　actual　electrical　conditions,　which　is　essential　to　the　precise　modeling　and　predicting　of　SiC　MOSFET　switching　performance.　Secondly,　a　segmented　characterization　method　of　Cds　is　proposed　to　deal　with　the　challenging　obstacles　on　the　modeling　of　nonlinear　capacitance　outside　miller　plateau　area　during　switching　process.　And　then,　an　accurate　capacitance　modeling　method　is　set　up　based　on　these　two　methods.　Finally,　the　proposed　method　is　verified　by　establishing　a　Spice　model　of　SiC　MOSFET,　and　a　double　pulse　test　(DPT)　experimental　platform　is　built　to　compare　with　the　simulation　results.　The　comparison　results　show　that　the　simulation　waveform　of　this　proposed　method　fits　better　with　the　experiment　one　than　the　previous　method,　which　indicates　the　high　performance　of　the　proposed　method.　©　2021　IEEE.